1. Field of the Invention
The present invention relates to an ion implantation method applied in producing a solid-state imaging device, a semiconductor device, or the like, a method of producing a solid-state imaging device using the ion implantation method, a solid-state imaging device, and an electronic apparatus such as a camera.
2. Description of the Related Art
Solid-state imaging devices are broadly divided into amplification-type solid-state imaging device represented by a complementary metal oxide semiconductor (CMOS) image sensor and a charge transfer-type solid-state imaging device represented by a charge coupled device (CCD) image sensor. These solid-state imaging devices are widely used in a digital still camera, a digital video camera, and the like. Recently, as a solid-state imaging device installed in a mobile device such as a camera cell phone or a personal digital assistant (PDA), a CMOS image sensor is often used from the standpoint of a low power supply voltage, electric power consumption etc.
A CMOS solid-state imaging device includes a pixel portion (imaging area) where a large number of pixels each including a photodiode functioning as a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix shape, and a peripheral circuit portion. Examples of the structure of the pixel transistors constituting a pixel include a four-transistor structure having a transfer transistor, a reset transistor, an amplifying transistor, and a selection transistor, and a three-transistor structure in which the selection transistor in the four-transistor structure is omitted. Each of the pixels is driven by a pixel-driving wiring extending in the horizontal direction. A signal of the pixel is an analog signal and is output to a vertical signal line extending in the vertical direction.
The peripheral circuit portion includes a control circuit, a vertical drive circuit, column signal-processing circuits, a horizontal drive circuit, an output circuit etc. The control circuit receives an input clock and data that directs an operational mode etc. and outputs data of internal information etc. of the solid-state imaging device. In addition, the control circuit supplies the vertical drive circuit, the column signal-processing circuits, and the horizontal drive circuit with necessary clocks and pulses.
The vertical drive circuit selects a pixel-driving wiring and supplies the selected pixel-driving wiring with a pulse for driving a pixel. When a certain pixel-driving wiring is driven, a row of pixels corresponding to the pixel-driving wiring is driven at the same time.
The column signal-processing circuit is provided for every pixel column. On receiving signals of pixels of each column, the corresponding column signal-processing circuit performs processes such as a correlated double sampling (CDS, a process of removing fixed pattern noise), a signal amplification, and an A-D conversion to the signals.
The horizontal drive circuit sequentially selects the column signal-processing circuits and leads signals of the column signal-processing circuits to a horizontal signal line. The output circuit processes signals of the horizontal signal line and outputs the processed signals. For example, the output circuit may perform only buffering or may perform a black-level adjustment, a correction of variations between columns, various types of digital signal processing, and the like before the buffering.
FIG. 24 shows a schematic cross-sectional structure of a pixel portion. In FIG. 24, only a portion of a semiconductor region is shown, and other components such as a multilayer wiring layer, an on-chip color filter, and an on-chip microlens are omitted. In a pixel portion 101, one pixel 104 is isolated by a p-type semiconductor well region 102 where pixel transistors are formed, and a p-type semiconductor well region (i.e., plug semiconductor well region) 103 disposed under the p-type semiconductor well region 102. The p-type semiconductor well region 103 corresponds to a pixel isolation region. Although not shown in the figure, the pixel transistors are formed in the p-type semiconductor well region 102. A photodiode PD functioning as a photoelectric conversion portion constituting the pixel 104 includes a p-type semiconductor region 105 disposed on the surface and an n-type semiconductor region 106 which is disposed under the p-type semiconductor region 105 and which accumulates signal charges (electrons). An n-type semiconductor region 107 which has a low impurity concentration is formed under the n-type semiconductor region 106 functioning as a charge accumulation region in order to widely collect the signal charges (electrons) generated by photoelectric conversion in a deep portion.
The p-type semiconductor well region 103, which is the pixel isolation region, functions as a barrier so that the signal charges (electrons) are not moved to the adjacent photodiode PD. Furthermore, a p-type semiconductor region 108 for preventing an interface at the reverse surface side from depleting is provided under the p-type semiconductor well region 103 and the n-type semiconductor region 107 having a low impurity concentration.
As shown in FIG. 25 (which is a cross-sectional view taken along line XXV-XXV in FIG. 24), the p-type semiconductor well region 103 is formed in a grid shape to isolate the pixels 104.
Japanese Unexamined Patent Application Publication No. 2006-93319 discloses a solid-state imaging device in which a p-type semiconductor region is used as an element isolation region of the device. Japanese Unexamined Patent Application Publication No. 10-116975 discloses a solid-state imaging device in which a p-type channel region formed by ion implantation is used as a channel stop region. Japanese Unexamined Patent Application Publication No. 2004-39832 discloses a solid-state imaging device in which an STI structure is used as element isolation. Japanese Unexamined Patent Application Publication No. 2006-216577 discloses a solid-state imaging device in which a deep p-type semiconductor region is used as an element isolation region.